The present invention generally relates to a timing system for use in a microprocessor for initiating microprocessor outputs onto and input sampling from an external bus in synchronism with a bus timing clock on the bus. The present invention more particularly relates to such a timing system which is configurable for providing the external bus with the bus timing clock or being driven by an externally generated bus timing clock. The timing system of the present invention is configured to provide the bus with the bus timing clock and when so configured, is also arranged to minimize the time required to provide an output onto the bus (clock to output time). The timing system is also configured to be readily driven by an externally generated bus timing clock.
Processing systems which incorporate at least one processor and at least one device, such as a memory, external to the microprocessor generally include an external bus to permit the microprocessor to perform external accesses. When such external accesses are required, such as when the microprocessor provides an output onto the external bus or samples an input from the external bus, the external accesses must be performed by the microprocessor in synchronism with the bus timing clock which controls the timing of the external bus. Such synchronization is required because the bus timing clock may or may not be at the same frequency as the microprocessor timing clocks and, in either case, is generally not in phase with the microprocessor timing clocks. In addition, such synchronization is further required because the external bus timing generally only permits microprocessor outputs onto the external bus when the bus clock is in a predetermined portion of its cycle, such as when the bus clock is at a high level, and only permits input sampling from the external bus when the external bus timing clock is in another predetermined portion of its clock cycle, such as when the bus timing clock is at a low level. Hence, microprocessors generally require a timing system for synchronizing external bus accesses with the bus timing clock which controls the timing of the external bus.
In one microprocessing system, the synchronizing timing depends on the occurrence of the rising edges of the bus timing clock. Upon a rising edge of the bus timing clock, the external bus is ready to receive outputs, such as data, from the microprocessor. The time required for the microprocessor to provide an output from the rising edge of the bus timing clock is referred to as the clock to output time and is an important parameter since, as the clock to output time is shortened, the time that the external system has for sampling the microprocessor outputs is lengthened. Also of importance is the set-up time which is the time from when an input to be sampled by the microprocessor is provided by the external bus to the next rising edge of the bus timing clock. As the set-up time is shortened, the time in which the external bus must hold the input data valid is decreased. Also, a shortened set-up time gives the external system more time to sample a responsive output from the microprocessor, such as when the microprocessor must change the state of the bus during the next bus timing clock cycle.
Microprocessors are also often required to generate the bus timing clock for the external bus and the external system in addition to generating its own internal timing clocks. The timing system of one known microprocessor is adapted to be coupled to an external clock source having a frequency twice that of the bus timing clock and the microprocessor internal timing clocks. In this microprocessor, the timing system uses the external clock to derive an intermediate clock from which it generates the bus timing clock. The bus timing clock is then used to generate the internal microprocessor timing clocks. While this configuration is satisfactory, the clock to output time is lengthened since the rising edges of the internal microprocessor clock controlling outputs is necessarily delayed with respect to the rising edges of the bus timing clock.
The timing systems of microprocessors are also called upon to be driven by an externally generated bus timing clock, as for example in multiprocessor systems. The aforementioned prior art processor still generates its own internal timing clocks in response to the externally generated bus timing clock. Unfortunately, the implementation of this system leaves much to be desired. For example, required internal duty cycles, to satisfy microprocessor speed path requirements, must be met. This problem is aggravated by the requirement that the externally generated bus timing clock be a CMOS input requiring TTL (transistor-transistor logic) level translation which skews the duty cycles from which the microprocessor internal timing clocks are derived. This makes it difficult for duty cycle requirements of the internal microprocessor timing clocks to be met for high frequency microprocessor operation.
There is therefore a need in the art for a new and improved timing system for use in a microprocessor for synchronizing microprocessor external accesses to the bus timing clock of an external bus. Such a timing system should be configured to be readily implemented to be driven by an externally generated bus timing clock. Such a timing system should be further configured for providing the external bus with the bus timing clock and, when so configured, should additionally be capable of reducing the clock to output times.